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| L64733/L64734 Tuner and Satellite Receiver Chipset Datasheet The L64733/34 chipset is designed specifically to meet the needs of satellite broadcast digital TV and is compliant with the European digital video broadcast (DVB-S) standard and the technical specifications for DSS systems. The chipset forms a complete "L-Band to bits" system. A typical application of the L64733/34 chipset is satellite digital TV reception in accordance with ETS 300 421. Figure 1 shows the L64733/34 chipset satellite receiver implemented in a typical satellite receiver set-top decoder box. Figure 1 Block Diagram of Set-Top Decoder Box Using the L64733/34 Chipset Optional DRAM 256K x 16 L64733/L64734 Chipset Satellite In RF Out (Loop Through) L64733 L64734 CO [7:0] Optional Decryption Engine / 16 Transport Demux 8 /8 / High-Speed Port Microprocessor Data and Address Bus /2 27 MHz VCXO Microprocessor / 8 Audio Oversampling Clock NTSC PAL S-Video L-Speaker R-Speaker PAL / NTSC Encoder CCIR601VIDEO / 8 Audio/Video Decoder Audio/Video PES SDRAM 256K x 64 256K x 32 PCM Audio DAC PCM AUDIO / 3 64/32 The L64733/34 chipset consists of the L64734 Satellite Receiver IC, the L64733 Tuner IC, and an on-chip synthesizer. Figure 2 shows a simplified block diagram of this chipset. August 2000 Copyright (c) 1999, 2000 by LSI Logic Corporation. All rights reserved. 1 Figure 2 Select RF Input RF Output L64733/34 Simplified Block Diagram L64733 RF Switch Synthesizer, Mixer, DownConverter Baseband Filter Control Signals Control Modules for Synthesizer and Filter IOUT QOUT L64734 Dual ADC Demodulator Host Microcontroller Microcontroller Interface Error Correction Descrambler MPEG Output The L64734: * generates control signals for the L64733 synthesizer, using frequency information programmed into the L64734 configuration registers controls the programming of the low-pass filters on the L64733 generates dual AGC control voltages for the two-stage automatic gain control on the L64733 IC. * * The L64733 Tuner IC directly down-converts the satellite signal from L-band to baseband. 2 L64733/L64734 Tuner and Satellite Receiver Chipset Figure 3 shows a more detailed chipset block diagram. Figure 3 Detailed Chipset Block Diagram L64733 Xtal Osc 4-7.26 MHz RF In RF Out Tank Circuit RF Switch Amp / by 8 Phase Detect. Charge Pump To External Loop Filter Quadrature Down-Converter VCO X2 DualModulus Prescaler PSOUT 2 90 Fc 2 2 2 FDOUB INSEL FLCLK QOUT PLLIN AGC1 AGC2 MOD L64734 Synthesizer Control Module AGC Control Carrier Loop Control BPSK/QPSK Demodulator Timing Loop Control Filter Control Module CPG DEMI Dual ADC Interpolator/Decimation Filter Matched Filter Output Control 1/T DEMQ Microcontroller Data and Address Bus Clk (from L64734 on-chip PLL) FEC Decoder Pipeline External Microcontroller Interface Microcontroller Data and Address Bus Channel Output (MPEG-2 Transport Stream) Descrambler ReedSolomon Decoder Convolutional Deinterleaver ReedSolomon Synchronizer Viterbi Decoder Viterbi Synchronizer L64733/L64734 Tuner and Satellite Receiver Chipset IOUT 2 3 The L64733 directly accepts the RF In L-Band signal input from the satellite LNB feed. The L64733 handles a fully loaded raster of transponder signals from 925 MHz to 2175 MHz. RF In is internally matched to 75 , and except for a DC-blocking capacitor, requires no matching network between the cable connector and the L64733 input pins. The L64733 uses the L64734 INSEL signal to select the appropriate RF function (Normal or Loop-Through mode). The RF signal goes to a variable gain stage, which is controlled by the L64734 AGC1 signal. The L64734 adjusts AGC1 in conjunction with AGC2 to maximize the SNR of the RF signal while maintaining proper levels at the baseband outputs (IOUT and QOUT). The signal then goes to two mixers in the quadrature demodulator. The mixers are fed with local oscillator signals that are offset by 90 degrees from one another. The quadrature demodulator performs a direct frequency conversion of the RF signal to baseband while splitting the signal into quadrature I and Q signal paths. The baseband signals pass through a pair of variable-gain amplifiers that are controlled by the AGC2 pin, which, in turn is controlled by the L64734. The signals are then filtered through a pair of 7th-order filters for anti-aliasing. The filter shape is 7th-order Butterworth, followed by a single-pole delay equalizer. The filter cut-off frequency, which is controlled by the L64734 FLCLK signal, is related to the baud rate. The filtered baseband output signals go to the differential output stages at IOUTp, IOUTn, QOUTp and QOUTn. The baseband outputs of the L64733 go to the L64734, where they are digitized by the analog-to-digital converter (ADC). The outputs then go to a BPSK/QPSK demodulator, where they are filtered. The demodulator then sends them to the L64734 FEC decoder pipeline, which outputs an MPEG-2 transport stream. The frequency synthesizer functionality is split between the L64733 and L64734. The Synthesizer Control Module resides on the L64734; it generates control signals for the L64733 Tuner IC frequency synthesizer. The Synthesizer Control Module also contains some of the programmable counters that are part of the synthesizer feedback loop. The L64733 contains many of the analog functions of the frequency synthesizer, as well as the RF local oscillator and crystal reference oscillator. Tuning oscillator signals are generated for the mixers in the 4 L64733/L64734 Tuner and Satellite Receiver Chipset range from 925-2175 MHz, with a 0.5 MHz step size when using a 4-MHz crystal reference. The on-chip VCO tuning frequency is 543 MHz to 1088 MHz. To tune channels from 925-1086 MHz, the L64734 disables the frequency doubler (X2 block) on the L64733. To tune channels from 1086 MHz to 2175 MHz, the L64734 enables the frequency doubler. The VCO requires an external resonant tank circuit, which includes varactor diodes to vary the frequency of oscillation. The VCO signal goes to the Prescaler block before it is passed to the L64734 differentially through the PSOUTp and PSOUTn pins. The L64734 MODp and MODn differential signals control the divider ratio for the Prescaler block. The L64734 dynamically changes the divide ratio to ensure that the tuning step size is not affected by the divider. The L64734 contains programmable counters to further divide the signal in frequency before the signal is fed back to the L64733 through the PLLINp and PLLINn pins. The crystal reference oscillator frequency is divided by eight, then fed to the phase detector. The phase detector generates a current signal proportional to the difference in phase between PLLINp, PLLINn, and the divided crystal frequency. A charge pump circuit (which controls pins CP, FB) and an external transistor (to buffer the L64733 against the tuning voltage of 28 V) generate the current. The current is filtered, fed through a discrete loop filter, and converted to a tuning voltage that drives the external varactor diodes for the VCO tank circuit. A complete frequency controlled loop is formed, and the VCO frequency can be varied by changing the frequency divider ratios in the L64734 registers. See Figure 7 on page 22 for more details regarding the external circuitry for the VCO, crystal oscillator, charge pump, tank circuitry, and entire frequency-controlled loop. The chipset provides maximum integration and flexibility for system designers at a minimum cost. The number of external components required to build a system is minimal because the synthesizer, variable rate filters, and clock and carrier loops are all integrated into the two devices. L64733/L64734 Tuner and Satellite Receiver Chipset 5 Features and Benefits System Features * * * * * * Direct down-conversion Integrated programmable cut-off low-pass filters for variable-rate operation Dual AGC for optimizing performance with respect to intermodulation and noise Integrated synthesizer Integrated quadrature amplitude and phase imbalance compensation RF loop-through Chipset Features * * * * * * * * * * * * * Supports DVB and DSS system specifications BPSK/QPSK demodulation rates from 1 to 45 Mbaud Matched filter (square root raised cosine filter with roll-off factor of 20% or 35%) Anti-aliasing filters for operation from 1 to 45 Mbaud without switching external SAW filters or the need for low-pass filters On-chip digital clock synchronization On-chip digital carrier synchronization, featuring a frequency sweep capability for signal acquisition Auto-acquisition demodulator mode and tuner control through an on-chip microcontroller Integrated Phase-Locked Loop (PLL) for clock synthesis, allowing the use of a fundamental mode crystal Fast channel switching mode Power estimation for AGC control Programmable Viterbi decoder module for rates 1/2, 2/3, 3/4, 5/6, 6/7, 7/8 Reed-Solomon decoder (204/188), (146/130) Auto-synchronization for Viterbi decoder 6 L64733/L64734 Tuner and Satellite Receiver Chipset * * * * * * * Programmable synchronization for deinterleaver, Reed-Solomon decoder, and descrambler Bit error monitoring for channel performance measurements Deinterleaver (DVB and DSS) Serial host interface compatible with the LSI Logic Serial Control bus interface Power-down mode On-chip dual differential 6-bit ADCs Supports Synchronous Parallel Interface protocol for FEC data output Chipset Interconnections Figure 4 shows the interconnections between the L64733 and L64734. Figure 4 Chipset Interconnection Diagram L64733 PLLINp PLLINn MODp MODn FDOUB FLCLK INSEL AGC1 AGC2 CPG1 CPG2 XTLOUT PSOUTp PSOUTn IOUTp IOUTn QOUTp QOUTn PLLINp PLLINn MODp MODn FDOUB FLCLK INSEL AGC1 AGC2 XCTR[0] XCTR[1] XOIN PSOUTp PSOUTn IVINp IVINn QVINp QVINn L64734 Control Signals Control Signals Prescaler Signals Prescaler Signals Channel Data Signals Channel Data Signals L64733/L64734 Tuner and Satellite Receiver Chipset 7 L64733 Signal Descriptions This section describes the L64733 signals. Figure 5 shows the interface diagram of the L64733. Names of signals that are active-LOW are designated with an "n" suffix (for example, ERROROUTn). Names of differential signals are designated with a "p" suffix for the noninverting side (for example, QOUTp), and with an "n" suffix for the inverting side (for example, QOUTn). Figure 5 L64733 Interface Diagram RFINn RF Signals RFINp RFOUT XTLn CFLT TANKn TANKp VRLO XTLp XTLOUT IOUTn IOUTp QOUTn QOUTp PSOUTn PSOUTp AGC1 AGC2 CPG1 CPG2 FDOUB FLCLK IDCn IDCp INSEL MODn MODp PLLINn PLLINp QDCn QDCp CP FB Oscillator Signals Control Signals Channel Data Signals Prescaler Signals Charge Pump Signals As shown in Figure 5, the L64733 has the following major interfaces: * * * * * * RF Oscillator Control Channel Data Prescaler Charge Pump 8 L64733/L64734 Tuner and Satellite Receiver Chipset The following signal descriptions are listed according to the major interface groups. Within each group, the signals are described in alphabetic order. RF Signals The L64733 can accept an RF input signal and loop it through to RFOUT. This is controlled by an on-chip RF switch. RFINn, RFINp RF Input Input The RFIN differential signals form the 75 input. Connect the RFINp signal through a series 100 pF capacitor to a 75 F video connector and the RFINn signal through a series 75 resistor and 100 pF capacitor to ground. RFOUT RF Output Output The RFOUT signal is a 75 output that is active when the INSEL input is deasserted. When active, the signal at RFOUT is a copy of the RFIN signal. Oscillator Signals The L64733 has two internal oscillators: a crystal oscillator and a tank oscillator. CFLT Bias Voltage Bypass Bidirectional See Figure 7 on page 22 for information on how to connect the CFLT pin. TANKn, TANKp Oscillator Tank Port Input See Figure 7 on page 22 for information on how to connect the TANKp and TANKn pins. VRLO Local Oscillator Regulator Bypass Bidirectional See Figure 7 on page 22 for information on how to connect the VRLO pin. Crystal Oscillator Port Input Connect the XTLp and XTLn pins as shown in Figure 7 on page 22. XTLn, XTLp L64733/L64734 Tuner and Satellite Receiver Chipset 9 XTLOUT Crystal Out Output This signal provides a buffered clock reference frequency for driving the L64734 XOIN pin. Control Signals The following signals, some of which are generated by the L64734 IC, control the mode of operation of the L64733 IC. AGC1 Automatic Gain Control 1 Input The AGC1 signal is a high-impedance input from the L64734; it controls the RF AGC circuitry. The AGC1 voltage range is from 0.5 V to 4.8 V. Automatic Gain Control 2 Input The AGC2 signal is a high-impedance input from the L64734; it controls RF AGC circuitry. Charge Pump Gain The CPG[2:1] signals set the charge pump gain according to the following table. Charge Pump Current (typ), mA CPG1 0 0 1 1 CPG2 0 1 0 1 FB HIGH 0.1 0.3 0.6 1.8 FB LOW -0.1 -0.3 -0.6 -1.8 AGC2 CPG[2:1] Input FDOUB Frequency Doubler Input When the FDOUB signal is asserted, the L64733 local oscillator frequency is internally doubled and fed to the mixers. When the FDOUB signal is deasserted, the oscillator frequency is not doubled before being fed to the mixers. Filter Clock Input The FLCLK signal is a low-amplitude, self-biased clock input. The frequency of the FLCLK signal multiplied by 16 is the baseband filter's -3 dB frequency. I-Channel DC Offset Correction Input Connect a 0.1 F (or larger) capacitor between the IDCp and IDCn signals. FLCLK IDCn, IDCp 10 L64733/L64734 Tuner and Satellite Receiver Chipset INSEL RF Port Input Select Input When the INSEL signal is asserted, the L64733 is in normal mode. When the INSEL signal is deasserted, the L64733 is in Loop-Through mode. In this mode, the RFIN signal is looped through to the RFOUT signal, and the L64733 local oscillator is shut off. MODn, MODp Prescaler Modulus Input The MOD differential signals form a PECL input that sets the prescaler modulus. When the MODp signal is positive with respect to the MODn signal, the prescaler modulus is set to 32 (divide by 32). When the MODn signal is positive with respect to the MODp signal, the prescaler modulus is set to 33 (divide by 33). PLLINn, PLLINp Phase Detector Input The PLLIN differential signals form the phase detector input and are connected to the L64734 PLLINp and PLLINn output signals. See the L64734 PLLINp and PLLINn descriptions in the subsection entitled "Synthesizer Control Interface" on page 19. QDCn, QDCp Q-Channel DC Offset Correction Input Connect a 0.1 F (or larger) capacitor between the QDCp and QDCn signals. Channel Data Signals This section describes the channel data signals from the L64733 to the L64734. IOUTn, IOUTp I-Channel Baseband Data Output The IOUT differential signals form the in-phase data provided to the L64734. QOUTn, QOUTp Q-Channel Baseband Data Output The QOUT differential signals form the quadrature-phase data provided to the L64734. L64733/L64734 Tuner and Satellite Receiver Chipset 11 Prescaler Signals The following signals are the prescaler outputs from the L64733 to the L64734. PSOUTn, PSOUTp Prescaler Output These differential signals are the L64733 prescaler outputs. The programmable counters on the L64734 are clocked on the rising edge of the PSOUT signal. Charge Pump Signals The following signals are outputs from the L64733 charge pump. CP FB Charge Pump Output Connect the CP signal as shown in Figure 7 on page 22. Feedback Charge Pump Transistor Drive Output Connect the FB signal as shown in Figure 7 on page 22. 12 L64733/L64734 Tuner and Satellite Receiver Chipset L64734 Signal Descriptions This section provides detailed information on the L64734 signals. Figure 6 shows the interface diagram of the L64734. Figure 6 L64734 Interface Diagram IVINp IVINn QVINp QVINn IBYPASS[5:0] QBYPASS[5:0] CLK XOIN XOOUT LCLK LP2 PLLAGND PLLVDD PLLVSS PCLK IDDTn RESET XCTR_IN XCTR[3:0] AGC1 AGC2 FLCLK INSEL BCLKOUT CO[7:0] COEn DVALIDOUT ERROROUTn FSTARTOUT INTn SADR[1:0] SDATA SCLK FDOUB PSOUTp PSOUTn MODp MODn PLLINp PLLINn VREF_LVDS RESO_LVDS VREFP VREFN ADCVSSI ADCVSSQ ADCVDDI ADCVDDQ VMID Channel Interface Channel Data Output Interface Channel Clock Interface Microcontroller Interface PLL Interface Synthesizer Control Interface Control Signals Interface AGC Control Interface Tuner Control Interface ADC Interface As shown in Figure 6, the L64734 has the following major interfaces: * * * * * Channel Channel Clock PLL Control Signals ADC L64733/L64734 Tuner and Satellite Receiver Chipset 13 * * * * * AGC Control Channel Data Output Microcontroller Synthesizer Control Tuner Control The following signal descriptions are listed according to the major interface groups. Channel Interface The Channel Interface is the input path to the L64734 satellite receiver. IVIN and QVIN are the I and Q streams, respectively, from the satellite tuner circuit. The CLK signal strobes in the data signals. IBYPASS[5:0] I Channel Data Input The IBYPASS[5:0] signals form the digital I channel data input bus, which supplies the I Stream to the L64734 when the ADC is bypassed. Bypass is controlled through the setting of particular register bits in the L64734. IVINn, IVINp I Channel Data Input These differential signals form the analog received I channel data input bus, which supplies the I stream to the L64734. QBYPASS[5:0] Q Channel Data Input The QBYPASS[5:0] signals form the digital received Q channel data input bus, which supplies the Q Stream to the L64734 when the ADC is bypassed. Bypass is controlled through the setting of particular register bits in the L64734. QVINn, QVINp Q Channel Data Input The QVINn and QVINp differential signals form the analog received Q channel data input bus, which supplies the Q stream to the L64734. 14 L64733/L64734 Tuner and Satellite Receiver Chipset Channel Clock Interface The Channel Clock Interface consists of the clock and crystal oscillator signals. CLK XOIN Input Clock Input This functionality has been assigned to the XOIN pin. Crystal Oscillator In Input The XOIN pin is used for a crystal oscillator or external reference clock input. A 15 MHz crystal is normally connected to the XOIN pin. This pin can also be driven by the XOOUT pin from L64733. When using an external ADC to strobe bypass data into the L64734, connect the clock input to this pin. Crystal Oscillator Out This is the crystal oscillator output pin. Output XOOUT Phase-Locked Loop (PLL) Interface The internal PLL generates the signals to operate the ADC, demodulator, and FEC modules. LCLK Decimated Clock Output Output The L64734 internal clock generation module generates the LCLK signal. LCLK is derived by dividing CLK by the value of the CLK_DIV2 register parameter. Input to VCO Input The LP2 signal is the input to the internal voltagecontrolled oscillator. It is normally connected to the output of an external RC filter circuit. PLL Clock Output Output The L64734 internal PLL clock synthesis module generates the PCLK signal. The PLL is driven by the reference crystal connected between the XOIN and XOOUT pins. The PLL clock synthesis module can be configured to generate a PCLK rate that is appropriate for all data rates. PLL Analog Ground Input PLLAGND is the analog ground pin for the PLL module; it is normally connected to the system ground plane. LP2 PCLK PLLAGND L64733/L64734 Tuner and Satellite Receiver Chipset 15 PLLVDD PLL Power Input PLLVDD is the power supply pin for the PLL module; it is normally connected to the system power (VDD) plane. PLL Ground Input PLLVSS is the ground pin for the PLL module; it is normally connected to the system ground plane. PLLVSS Control Signals Interface The Control Signals interface controls the operation of the L64734; it is not associated with any particular interface. IDDTn Test Input The IDDTn pin is an LSI Logic internal test pin. Tie the IDDTn pin LOW for normal operation. Reset Input This active-HIGH signal resets all internal data paths. Reset timing is asynchronous to the device clocks. Reset does not affect the configuration registers. Control Input Input The XCTR_IN pin is an external input control pin. It is sensed by reading the XCTR_IN register bit. Control Output/Sync Status Flag Output This signal indicates the synchronization status for one of three synchronization modules in the L64734 or the XCTR[3] field in Group 4, APR 55. The modules are the Viterbi decoder, Reed-Solomon deinterleaver (DI/RS), and descrambler. For any of the three synchronization outputs, asserting the XCTR[3] signal indicates that synchronization has been achieved for the sync module chosen using the SSS[1:0] register bits. When deasserted, the signal indicates an out-ofsynchronization condition. Control Output Output The XCTR[2:0] pins are external output control pins. They are set by programming particular register bits. XCTR[2] is mapped to CPG1, and XCTR[0] is multiplexed with CPG2, when used with the L64733 Tuner IC. When the on-chip serializer is used to generate a serial 2- or 3-wire protocol on the XCTR[2:0] pins, the mapping is XCTR[2] = EN, XCTR[1] = SCL, and XCTR[0] = SDA. RESET XCTR_IN XCTR[3] XCTR[2:0] 16 L64733/L64734 Tuner and Satellite Receiver Chipset Analog-to-Digital Converter (ADC) Interface The ADC module converts the incoming IVIN and QVIN signals into an internal 6-bit digital representation for processing. The following pins support the ADC module. ADCVDDI/Q ADC Power Input These are the analog power supply pins for the ADC module; they are normally connected to the system power (VDD) plane. ADC Analog Ground Input These are the analog ground pins for the ADC module; they are normally connected to the system ground plane. Reference Voltage, Positive Input/Output ADC reference voltage generated by the on-chip bandgap-based generator. Bypass to GND using a 0.1 F capacitor. Reference Voltage, Negative Input/Output ADC reference voltage generated by the on-chip bandgap-based generator. Bypass to GND using a 0.1 F capacitor. Reference Voltage, Middle Input/Output ADC reference voltage generated by the on-chip bandgap-based generator. Bypass to GND using a 0.1 F capacitor. ADCVSSI/Q VREFP VREFN VMID AGC Control Interface The AGC Control interface contains signals used for power control. AGC1, AGC2 Power Control Signals Output The AGC1 and AGC2 signals are the positive modulated output used for power control. These signals can each drive an external passive RC filter that feeds a gain control stage for dual-stage AGC. For a single-stage AGC, AGC1 can be used. L64733/L64734 Tuner and Satellite Receiver Chipset 17 Channel Data Output Interface The Channel Data Output interface is the output path from the L64734. It is typically connected to the input of the transport demultiplexer in a set-top decoder application. BCLKOUT Byte Clock Out Output This signal indicates valid data bytes on the CO[7:0] bus when the L64734 is in Parallel Channel Output mode. This signal cycles once every valid output data byte. It is used by the transport demultiplexer to latch output data from the L64734 at the BCLKOUT rate. Disregard the BCLKOUT signal when the L64734 is in Serial Channel Output mode. Channel Data Out Output The CO[7:0] signals form the decoded output data port. When the OF bit is 1 (Group 4, APR17), the L64734 operates in the Parallel Channel Output mode. In this mode, the L64734 outputs the channel data as eight-bitwide parallel data on the CO[7:0] signals. In Serial Channel Output mode (OF = 0), the L64734 outputs the channel data as serial data on CO[0]. The data is latched on every bit clock cycle. The chronological ordering in Serial Channel output mode is: MSB oldest, LSB newest. Channel Output Enable Input When asserted, the COEn signal enables the ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, and FSTARTOUT signals. Operation of the receiver continues regardless of the state of the COEn signal. Valid Data Out Output The DVALIDOUT signal indicates that the CO[7:0] signals contain the corrected channel data. New data is valid on the CO[7:0] signals when the DVALIDOUT signal is asserted. DVALIDOUT is not asserted during the propagated check and GAP bytes. The DVALIDOUT signal is deasserted after the FEC_RST register bit (Group 4, APR 55) is set to 1. CO[7:0] COEn DVALIDOUT ERROROUTn Error Detection Flag Output The L64734 asserts the ERROROUTn signal at the beginning of any frame that contains an uncorrectable error; it deasserts ERROROUTn at the end of the frame 18 L64733/L64734 Tuner and Satellite Receiver Chipset if the error condition is removed. The ERROROUTn signal is exactly aligned with the output data stream; it is asserted after the FEC_RST register bit is set. FSTARTOUT Frame Start Output Output The L64734 asserts the FSTARTOUT signal during the first bit of every frame with valid data in Serial Channel output mode, and during the first byte in Parallel Channel output mode. FSTARTOUT is valid only when the DVALIDOUT signal is asserted. The FSTARTOUT signal is deasserted after the FEC_RST register bit is set. Microcontroller Interface The Microcontroller interface connects the L64734 to an external microcontroller. INTn Interrupt Output The L64734 asserts INTn when an internal, unmasked interrupt flag is set. The INTn signal remains asserted as long as the interrupt condition persists and the interrupt flag is not masked. Serial Address Input The SADR[1:0] signals are the two programmable bits of the serial address for the L64734. Serial Clock Bidirectional This is the serial clock pin for a two-wire serial protocol. Serial Data Bidirectional This is the serial data pin for a two-wire serial protocol. SADR[1:0] SCLK SDATA Synthesizer Control Interface The Synthesizer Control interface lets the L64734 control the L64733 frequency synthesizer. FDOUB Frequency Doubler Output When FDOUB is asserted, the frequency doubler on the L64733 Tuner IC is enabled. When FDOUB is deasserted, the frequency doubler is disabled. This output is set by register programming. L64733/L64734 Tuner and Satellite Receiver Chipset 19 MODn, MODp Modulus Selector Output These signals are low-voltage differential signals from the L64734 modulus selector programmable counter (A). The signals are clocked by PSOUT. A positive MODp with respect to MODn selects a divide by 32 at the dual modulus prescaler on the L64733 Tuner IC. A negative MODp with respect to MODn selects a divide by 33. Counter A can be programmed to count down from a particular value by register bit programming. PLLINn, PLLINp PLL Differential Counter M Output These signals are low-voltage differential signals from the L64734 programmable synthesizer counter (M). The signals are clocked by PSOUT. PLLINp is positive with respect to PLLINn for one PSOUT cycle. The repetition rate is 0.5 MHz for a 4 MHz reference crystal. The counter M can be programmed to count down from a particular value by register bit programming. PSOUTn, PSOUTp Prescaler Output Output These signals are differential signals to the L64734 from the L64733. The programmable counters on the L64734 are clocked on the rising edge of the PSOUT signal. RESO_LVDS LVDS Buffers Precision Resistor Output The RESO_LVDS output must be connected to a resistor (6.8 k 5%) that controls the swing of the LVDSOUT buffers used to drive the differential signals MODp, MODn, and PLLINp, PLLINn. Connect the other side of the resistor to ground. VREF_LVDS LVDS Buffers Reference Voltage Input The VREF_LVDS input is a 1.2 V 10% voltage level that controls the common mode voltage of the LVDSOUT buffers used to drive the differential signals MODp, MODn, and PLLINp, PLLINn. 20 L64733/L64734 Tuner and Satellite Receiver Chipset Tuner Control Interface The Tuner Control interface contains signals that control the L64733 Tuner IC. FLCLK Filter Control Clock Output FLCLK is the output of a programmable integer value divider clocked by the demodulator sampling clock, PCLK. The division ratio can be programmed with register bits. The frequency of FLCLK multiplied by 16 is the 3 dB cutoff of the programmable low-pass filters on the L64733. RF Input Select Output When INSEL is asserted, the L64733 tuner selects the normal mode. When INSEL is deasserted, the L64733 selects the Loop-Through mode. INSEL Typical Operating Circuit Figure 7 is a diagram of a typical operating circuit for the chipset, including external components. Not all external components are shown. See the L64733/34 Evaluation Board User's Guide for complete schematic details. L64733/L64734 Tuner and Satellite Receiver Chipset 21 Figure 7 28 V 22K Typical Operating Circuit 22 L64733/L64734 Tuner and Satellite Receiver Chipset 75 100 pF 75 1K 22 nF 10K 6.8K 100 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1nF Varactors (2) Stripline Inductors (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SADR[1] SADR[0] VDD VSS SDATA SCLK INTn RESET VDD VSS PSOUTn PSOUTp VDD VSS PLLINn PLLINp RESO_LVDS VREF_LVDS MODn MODp BC847 100 pF 1K 20 20 VDD VSS VCC 47 pF 0.2 F 180 pF 180 pF 6 MHz 1 2 3 4 5 6 7 8 9 10 11 12 0.1 F 75 100 pF VCC CFLT XTLn XTLp GND1 VCC RFINn RFINp GND1 GNDSUB1 QDCn QDCp L64733 PLLINn PLLINp MODn MODp GND1 IOUTp IOUTn VCC QOUTp QOUTn FDOUB FLCLK 36 35 34 33 32 31 30 29 28 27 26 25 47K AGC Filter 0.1 F 100 pF 0.01 F ADCVDDI IVINp IVINn ADCVSSI VREFP VMID VREFN ADCVDDQ QVINp QVINn ADCVSSQ VDD VSS FDOUB FLCLK INSEL AGC2 AGC1 VDD VSS XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN VDD VSS IBYPASS[5] L64734 VSS VDD PLLVSS LP2 PLLAGND PLLVDD PCLK LCLK VSS VDD CO[0] CO[1] CO[2] CO[3] VSS VDD CO[4] CO[5] CO[6] CO[7] VSS VDD BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn VSS VDD COEn IDDTn 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 37 38 39 40 41 42 43 44 45 46 47 48 PSOUTp PSOUTn VCC GND1 GND1 TANKn VRLO TANKp VCC GND1 FB CP INSEL AGC2 AGC1 CPG2 XTLOUT VCC CPG1 RFOUT GND1 GNDSUB1 IDCp IDCn 24 23 22 21 20 19 18 17 16 15 14 13 XOOUT XOIN VSS CLK VDD QBYPASS[0] QBYPASS[1] VSS VDD QBYPASS[2] QBYPASS[3] QBYPASS[4] QBYPASS[5] IBYPASS[0] VSS VDD IBYPASS[1] IBYPASS[2] IBYPASS[3] IBYPASS[4] Notes: 1. The ground connections for the L64733 are provided through a metal plate under the IC, rather than by direct connection of the ground pins to the PCB. 2. Not all external components are shown. Refer to the L64733/34 Evaluation Board User's Guide for complete details. 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Specifications This section contains the electrical, timing, and mechanical specifications for the L64733/34 chipset. L64733 Electrical Specifications This section contains the electrical parameters for the L64733. Table 1 lists the absolute maximum values. Exceeding the values listed can cause damage to the L64733. Table 2 gives the recommended operating supply voltage and temperature. Table 3 gives the DC characteristics. Table 4 gives the AC characteristics. Table 5 summarizes the pins. Table 1 Symbol VCC - - - - - ja - L64733 Absolute Maximum Rating (Referenced to VSS) Parameter DC Supply Voltage Continuous power dissipation up to +70 C Derating above +70 C Operating temperature Junction temperature Storage Temperature Junction to Ambient Thermal Resistance2 Limits1 -0.5 to +7.0 1.05 2 0 to +70 +150 -65 to +165 27.6 +300 Units V W mW/C C C C C/watt C Lead temperature (soldering 10 sec) 1. Note that the ratings in this table are those beyond which permanent device damage is likely to occur. Do not use these values as the limits for normal device operation. 2. The junction to ambient thermal resistance is for the ePad TQFP package, for a four-layer board. L64733/L64734 Tuner and Satellite Receiver Chipset 23 Table 2 Recommended Operating Conditions Limits1 Units 5 5% 70 V C Symbol Parameter VDD TA DC Supply Voltage Operating Ambient Temperature Range (Commercial) 1. For normal device operation, adhere to the limits in this table. Sustained operation of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. Device functionality to stated DC and AC limits is not guaranteed if recommended operating conditions are exceeded. Table 3 Parameter DC Characteristics of the L647331 Condition Min Typ Max Units Power Supply Power Supply Voltage Power Supply Current Digital Control Inputs - CPG1, CPG2, INSEL, FDOUB Input Logic Level HIGH Input Logic Level LOW Input Bias Current Pin at 2.4 V 2.4 0 -15 - - - - 0.5 10 V V A All DC specs met 4.75 - 5.0 190 5.25 220 V mA Slew-Limited Digital Clock Inputs - FLCLK FLCLK Input Level LOW FLCLK Input Level HIGH FLCLK Input Resistance/Leakage Current 50 K series resistor between L64734 and FLCLK pin. L64734 generates normal CMOS levels - 1.85 -1 - - - 1.45 - 1 V V A Fast Digital Clock Inputs - MODp, MODn, PLLINp, PLLINn MODp, MODn, PLLINp, PLLINn Common Mode Input Range (VCM) MODp, MODn, PLLINp, PLLINn Input Voltage LOW MODp, MODn, or PLLINp, PLLINn differential swing around VCM. Need external 100 termination 1.08 1.2 1.32 V - - -100 mV (Sheet 1 of 3) 24 L64733/L64734 Tuner and Satellite Receiver Chipset Table 3 Parameter DC Characteristics of the L647331 (Cont.) Condition MODp, MODn, or PLLINp, PLLINn differential swing around VCM. Need external 100 termination MODp, MODn, PLLINp, PLLINn Min 100 Typ - Max - Units mV MODp, MODn, PLLINp, PLLINn Input Voltage HIGH MODp, MODn, PLLINp, PLLINn Input Current -5 - +5 A Digital Clock Outputs - PSOUTp, PSOUTn PSOUTp, PSOUTn Common Mode Output Range (VCM) PSOUTp, PSOUTn Output Voltage LOW PSOUTp, PSOUTn Output Voltage HIGH Synthesizer Prescaler Ratio MOD = HIGH MOD = LOW Reference Divider Ratio Charge Pump Output HIGH Current (at FB) CPG1, CPG2 = 0, 0 CPG1, CPG2 = 0, 1 CPG1, CPG2 = 1, 0 CPG1, CPG2 = 1, 1 Charge Pump Output LOW Current (at FB) CPG1, CPG2 = 0, 0 CPG1, CPG2 = 0, 1 CPG1, CPG2 = 1, 0 CPG1, CPG2 = 1, 1 Charge Pump Output Leakage Current Charge Pump Positive-toNegative Current Matching (Sheet 2 of 3) FB self-biased 32 33 8 0.08 0.24 0.48 1.44 -0.12 -0.36 -0.72 -2.16 -25 -5 - - - 0.1 0.3 0.6 1.8 -0.1 -0.3 -0.6 -1.8 - - 32 33 8 0.12 0.36 0.72 2.16 -0.08 -0.24 -0.48 -1.44 25 5 - - - mA mA mA mA mA mA mA mA nA % PSOUTp, PSOUTn differential swing around VCM. Driving LSI PECL Load (10 A) PSOUTp, PSOUTn differential swing around VCM. Driving LSI PECL Load (10 A) 2.16 - 2.4 -215 2.64 -150 V mV 150 215 - mV L64733/L64734 Tuner and Satellite Receiver Chipset 25 Table 3 Parameter DC Characteristics of the L647331 (Cont.) Condition Min 100 Typ - Max - Units A Charge Pump Output Transistor Base Current Drive Analog Control Inputs - AGC1, AGC2 Input Bias Current 1 V < Pin < 4 V -50 - 50 A Baseband Outputs - IOUTp, IOUTn, QOUTp, QOUTn Output Swing IOUTp, IOUTn, QOUTp, QOUTn Common Mode Voltage IOUTp, IOUTn, QOUTp, QOUTn DC Offset Voltage (Sheet 3 of 3) 1. For symbol rates below 15 MSymbols/s, the maximum input power might be subject to shifting down by roughly 10 * log(15/Rs[MSymbols/s]) dB due to channel bandwidth reduction. Loaded with 2 K differential across IOUTp, IOUTn, and QOUTp, QOUTn 1 0.65 - - - 0.85 VPP V -50 - 50 mV 26 L64733/L64734 Tuner and Satellite Receiver Chipset Table 4 Parameter AC Characteristics of the L64733 Condition Min Typ Max Units RF Front End RFIN Input Frequency Range RFIN Single-Carrier Input Power AGC1 Range AGC2 Range RFIN referred IP3 (front-end contributions) Meets all following AC specs RF level needed to produce 0.59 VPP 1 V < AGC1 < 4 V 1 V < AGC2 < 4 V AGC1 gain set for -25 dBm input level (0.59 VPP output), and AGC2 set to maximum gain (VAGC2 = 1 V). 2 signals at FLO + 32 MHz, FLO + 72 MHz @2175 MHz @1550 MHz @925 MHz 925 -65 50 19 - - - - - - - 3 7 8 2175 -251 - - - - - MHz dBm dB dB dBm dBm dBm Baseband 1 dB Compression Point RFIN Referred IP2 Noise Figure RFIN Worst Case Return Loss LO Leakage Power at RFIN Second Harmonic Rejection Half-Harmonic Rejection and x 1.5 Harmonic Rejection1, 2 Loop Through Gain IOUTp, IOUTn, QOUTp, QOUTn have 1 signal within filter BW PRFIN = -25 dBm, FLO = 951 MHz At maximum gain AGC1, AGC2 Complex "75 source" subject to board, connector parasitics. 950 MHz to 2150 MHz, subject to board layout Due to LO-generated 2nd harmonic Due to RFIN-generated 2nd harmonic 2 - - - - 27 - - 15.5 11.5 11 -65 - 27 - - - - - - - VPP dBm dB dB dBm dB dB @2175 MHz @1550 MHz @925 MHz - 2.5 1.8 0.8 - dB (Sheet 1 of 3) L64733/L64734 Tuner and Satellite Receiver Chipset 27 Table 4 Parameter AC Characteristics of the L64733 (Cont.) Condition At PRFIN = -25 dBm @2175 MHz @1550 MHz @925 MHz Min - Typ 5 7 9 12.0 8 Max - Units dBm RFIN referred IP3 (when Loop-Through enabled) Noise Figure Worst-Case Return Loss Baseband IOUTp, IOUTn, QOUTp, QOUTn Differential Output Voltage Swing IOUTp, IOUTn, QOUTp, QOUTn Output Impedance Baseband Highpass -3 dB Point LPF Nominal Cutoff Frequency Range LPF Nominal Fc Baseband Frequency Response LPF Cutoff Frequency Accuracy Quadrature Gain Error Quadrature Phase Error Synthesizer Crystal Frequency Range XTLOUT Voltage Levels XTLOUT DC Level (Sheet 2 of 3) - Subject to board and connector parasitics - - - dB dB 2 k differential load, IOUTp, IOUTn, QOUTp, QOUTn. Expect 20 pF from each pin to GND Per side, IOUTp, IOUTn, QOUTp, QOUTn. To 200 MHz 0.22 F caps connected from IDCp to IDCn, and QDCp to QDCn. Fc is -3 dB point of filter 1 - - VPP - - 50 s - 8 - - - 14.5 * FFLCLK + 1 - 750 33 - 0.5 Hz MHz - dB Deviation from ideal 7th-order Butterworth, measure to F - 3 dB x 0.7. Include front-end tilt effects Measured -3 dB point @8 MHz @31.4 MHz -0.5 -5.5 -10 - - - - - - 5.5 10 1.2 4 % % dB Deg Includes effects from baseband filters Measure at 125 kHz 4 Measured on 10 pF // 1 M 0.8 - - 1.0 2.0 7.26 1.3 - MHz VPP V 28 L64733/L64734 Tuner and Satellite Receiver Chipset Table 4 Parameter AC Characteristics of the L64733 (Cont.) Condition Must assert MOD level within this time period to ensure that the next PSOUT period gives correct count. Delay is with respect to rising edge of PSOUT (previous count). Min - Typ - Max 8.5 Units ns MODp, MODn Delay PLLINp, PLLINn and With respect to rising edge of PSOUT. MODp, MODn Hold Time This means that PSOUT need not continue to be asserted after MOD has given correct count. Local Oscillator LO Tuning Range LO Phase Noise, Including Doubler. Subject to LC tank implementation. 1 kHz offset. Depends on PLL loop gain. 10 kHz offset. Depends on PLL loop gain. 100 kHz offset LO Buffer Frequency Range when overdriven by external LO LO Input Port VSWR Over Band, when overdriven by external LO Required external LO Input Power Range (Sheet 3 of 3) FDOUB = LOW 0 - - ns 543 - - - 925 - -55 -75 -95 - 1180 - - - 2175 MHz dBc/ Hz dBc/ Hz dBc/ Hz MHz 925 MHz < FLO < 2175 MHz. Assume series resistors to TANKp and TANKn pins Differential drive into TANKp, TANKn. 50 source. - - 2:1 - -15 - -5 dBm 1. x 1.5 harmonic rejection for FLO = 725 MHz. 2. The L63733 is available with the half-harmonic specification guaranteed to 38 dB typical. Contact your LSI Logic sales representative for further information. L64733/L64734 Tuner and Satellite Receiver Chipset 29 Table 5 Mnemonic AGC1 AGC2 CFLT CP CPG[2:1] FB FDOUB FLCLK IDCp IDCn INSEL IOUTp IOUTn MODp MODn PLLINp PLLINn PSOUTp PSOUTn QDCp QDCn QOUTp QOUTn RFINp L64733 Pin Description Summary Description Automatic Gain Control 1 Automatic Gain Control 2 Bias Voltage Bypass Charge Pump Charge Pump Gain Feedback Charge Pump Transistor Drive Frequency Doubler Filter Clock I-Channel DC Offset Correction (noninverting) I-Channel DC Offset Correction (inverting) RF Port Input Select I-Channel Baseband Data (noninverting) I-Channel Baseband Data (inverting) Prescaler Modulus (noninverting) Prescaler Modulus (inverting) Phase Detector (noninverting) Phase Detector (inverting) Prescaler (noninverting) Prescaler (inverting) Q-Channel DC Offset Correction (noninverting) Q-Channel DC Offset Correction (inverting) Q-Channel Baseband Data (noninverting) Q-Channel Baseband Data (inverting) RF Input (noninverting) Type Input Input Bidirectional Output Input Output Input Input Input Input Input Output Output Input Input Input Input Output Output Input Input Output Output Input (Sheet 1 of 2) 30 L64733/L64734 Tuner and Satellite Receiver Chipset Table 5 Mnemonic RFINn RFOUT TANKp TANKn VRLO XTLp XTLn XTLOUT L64733 Pin Description Summary (Cont.) Description RF Input (inverting) RF Output (Loop-Through) Oscillator Tank Port (noninverting) Oscillator Tank Port (inverting) Local Oscillator Regulator Bypass Crystal Oscillator Port (noninverting) Crystal Oscillator Port (inverting) Crystal Out Type Input Output Input Input Bidirectional Input Input Output (Sheet 2 of 2) L64734 Electrical Specifications This section contains the electrical parameters for the L64734. Table 6 lists the absolute maximum values. Exceeding the values listed can cause damage to the L64734. Table 7 gives the recommended operating supply voltage and temperature conditions. Table 8 shows the pin capacitance. Table 9 gives the DC characteristics. Table 10 summarizes the pins. Table 6 L64734 Absolute Maximum Rating (Referenced to VSS) Limits1 -0.3 to +3.9 V -1.0 to VDD +0.3 -1.0 to 6.5 10 -40 to +125 Units V V V mA C Symbol Parameter VDD VIN VIN IIN TSTG DC Supply Voltage LVTTL Input Voltage 5 V Compatible Input Voltage DC Input Current Storage Temperature Range (Plastic) 1. Note that the ratings in this table are those beyond which permanent device damage is likely to occur. Do not use these values as the limits for normal device operation. L64733/L64734 Tuner and Satellite Receiver Chipset 31 Table 7 L64734 Recommended Operating Conditions Limits1 +3.14 to 3.47 0 to +70 +125 21.7 5 Units V C C C/watt C/watt Symbol Parameter VDD TA Tj ja jc DC Supply Voltage Operating Ambient Temperature Range (Commercial) Junction Temperature Junction to Ambient Thermal Resistance2 Junction to Case Thermal Resistance3 1. For normal device operation, adhere to the limits in this table. Sustained operation of a device at conditions exceeding these values, even if they are within the absolute maximum rating limits, can result in permanent device damage or impaired device reliability. Device functionality to stated DC and AC limits is not guaranteed if recommended operating conditions are exceeded. 2. The junction to ambient thermal resistance is for the PQFPt (U4) package, for a four-layer board. 3. The junction to case thermal resistance is valid only for measurements in an isothermal environment including the board and package. Table 8 Symbol CIN COUT L64734 Capacitance Parameter1 Input Capacitance Output Capacitance Max 5 5 Units pF pF 1. Measurement conditions are VIN = 3.3 V, TA = 25 C, and clock frequency = 1 MHz. 32 L64733/L64734 Tuner and Satellite Receiver Chipset Table 9 Symbol VDD VIL VIH DC Characteristics of the L64734 Parameter Supply Voltage Input Voltage LOW Input Voltage HIGH LVTTL Com/Ind/Mil Temp Range 5 V compatible Condition1 Min 3.0 VSS -0.5 2.0 2.0 - VDD = Max, VIN = VDD or VSS VIN = VSS VIN = VDD IOH = -1.0, -2.0, -4.0, -6.0, -8.0, -12.0 mA IOH = 1.0, 2.0, 4.0, 6.0, 8.0, 12.0 mA VDD = Max, VOUT = VSS or 3.5 V VIN = VDD or VSS - -10 -62 -62 2.4 - -10 - 290 Typ 3.3 - - - 1.4 1 -215 -215 - 0.2 1 Max 3.6 0.8 VDD + 0.3 5.5 2.0 10 -384 -384 VDD 0.4 10 2 - Units V V V V V A A A V V A mA mA VT IIL IIPU IIPD VOH VOL IOZ IDD ICC Switching Threshold Input Current Leakage Input Current Leakage with Pull-up Input Current Leakage with Pull-down Output Voltage HIGH Output Voltage LOW 3-State Output Leakage Current Quiescent Supply Current Dynamic Supply Current 20 Mbaud, rate = 3/4, VDD = 3.3 V, Fs = 75 MHz Midpoint of PSOUTp, PSOUTn inputs Input Voltage HIGH level (DC) PSOUTp - PSOUTn = 50 mV VCM VIH_PECL - VCM + 50 mV 2.4 - - - V V (Sheet 1 of 2) L64733/L64734 Tuner and Satellite Receiver Chipset 33 Table 9 Symbol VIL_PECL IIL_PECL IIH_PECL DC Characteristics of the L64734 (Cont.) Parameter Input Voltage LOW level (DC) Input LOW current Input HIGH current Condition1 PSOUTp - PSOUTn = 50 mV VIN = VSS VIN = VDD Min - -10 - - On PLLINp/PLLINn, MODp/MODn signals On PLLINp/PLLINn, MODp/MODn signals 1.253 1.030 Typ - - - 1.2 1.373 1.032 Max VCM -50 mV - +10 - 1.437 1.059 Units V A A V V V VRESO_LVDS Output Voltage on pin RESO_LVDS VOH_LVDS VOL_LVDS Output Voltage HIGH level (DC) Output Voltage LOW level (DC) (Sheet 2 of 2) 1. Specified at VDD = 3.3 V 5% at ambient temperature over the specified range. Table 10 Mnemonic ADCVDDI/Q ADCVSSI/Q AGC1, AGC2 BCLKOUT CLK CO[7:0] COEn DVALIDOUT L64734 Pin Description Summary Description ADC Power ADC Analog Ground Power Control Byte Clock Out Input Clock Channel Data Out Channel Output Enable Valid Data Out Error Detection Flag Frequency Doubler Type Input Input Outputs Output Input Output Input Output Output Output ERROROUTn FDOUB (Sheet 1 of 3) 34 L64733/L64734 Tuner and Satellite Receiver Chipset Table 10 Mnemonic FLCLK FSTARTOUT IBYPASS[5:0] IDDTn INSEL INTn IVINn, IVINp LCLK LP2 L64734 Pin Description Summary (Cont.) Description Filter Control Clock Frame Start Output I Channel Data (ADC bypassed) Test RF Input Select Interrupt I Channel Data Decimated Clock Output Input to VCO Modulus Selector PLL Clock Output PLL Analog Ground PLL Differential Counter M PLL Power PLL Ground Type Output Output Input Input Output Output Input Output Input Outputs Output Input Outputs Input Input Outputs Input Input Input Output Input Bidirectional Bidirectional Input MODp, MODn PCLK PLLAGND PLLINp, PLLINn PLLVDD PLLVSS PSOUTp, PSOUTn Prescaler Output QBYPASS[5:0] QVINn, QVINp RESET RESO_LVDS SADR[1:0] SCLK SDATA VREF_LVDS (Sheet 2 of 3) Q Channel Data (ADC bypassed) Q Channel Data Reset LVDS Buffers Precision Resistor Serial Address Serial Clock Serial Data LVDS Buffers Reference Voltage L64733/L64734 Tuner and Satellite Receiver Chipset 35 Table 10 Mnemonic VREFP VREFN VMID XCTR_IN XCTR[3:0] XOIN XOOUT L64734 Pin Description Summary (Cont.) Description Reference Voltage, Positive Reference Voltage, Negative Reference Voltage, Middle Control Input Control Output/Sync Status Flag Crystal Oscillator In Crystal Oscillator Out Type Input/Output Input/Output Input/Output Input Output Input Output (Sheet 3 of 3) L64734 AC Timing This section includes AC timing information for the L64734. During AC testing, HIGH inputs are driven to 3.0 V, and LOW inputs are driven to 0 V. For transitions between HIGH, LOW, and invalid states, timing measurements are made at 1.5 V, as shown in Figure 8. Figure 8 AC Test Load and Waveform for Standard Outputs Test Point Output CL = 15 pF 1.5 V For 3-state outputs, timing measurements are made from the point at which the output turns ON or OFF. An output is ON when its voltage is greater than 2.5 V or less than 0.5 V. An output is OFF when its voltage is less than VDD - 0.5 V or greater than 0.5 V, as shown in Figure 9. 36 L64733/L64734 Tuner and Satellite Receiver Chipset Figure 9 Test Point AC Test Load and Waveforms for 3-State Outputs Iref = 20 mA Output Vref = 1.5 V Vref 2.5 V 0.5 V VDD - 0.5 V 0.5 V 55 pF Iref = -20 mA Synchronous timing is shown in Figure 10. Synchronous inputs must have a setup and hold relationship with respect to the clock signal that samples them. Synchronous outputs have a delay from the clock edge that asserts them. Figure 10 L64734 Synchronous AC Timing 1 2 PCLK BCLKOUT 5 INPUTS 6 OUTPUTS 4 3 The reset pulse requirements are shown in Figure 11. Figure 11 L64734 RESET Timing Diagram 7 RESET 8 L64733/L64734 Tuner and Satellite Receiver Chipset 37 Figure 12 shows the relationship of the L64734 3-state signals to the COEn signal. Figure 12 COEn 9 CO FSTARTOUT ERROROUTn DVALIDOUT BCLKOUT 9 L64734 Bus 3-State Delay Timing Figure 13 shows the relationship of the L64733 PSOUTp and PSOUTn prescaler signals to the signals fed back to the L64733 from the L64734 to control the synthesizer. Figure 13 L64734 Synchronous AC Timing - Synthesizer Control 10 11 PSOUTn PSOUTp 13 PLLINp, MODp PLLINn, MODn 12 38 L64733/L64734 Tuner and Satellite Receiver Chipset The numbers in the first column of Table 11 refer to the timing parameters shown in the preceding figures. All parameters in the timing tables apply for TA = 0 C to 70 C and a capacitive load of 15 pF. Table 11 Parameter 1 2 3 4 5 tCYCLE tPWH tPWL tS tH L64734 AC Timing Parameters Description Clock Cycle for PCLK Clock Pulse Width HIGH Clock Pulse Width LOW Input Setup Time to CLK Input Hold to CLK Output Delay from PCLK, serial mode Output Delay from BCLKOUT, parallel mode Reset Pulse Width HIGH Wake-Up Time Delay from COEn Min 11.1 6 5 4 4 3 3 3 280 - 14 6 6 4 Max 33.31 - - - - 8 - - - 6 35 - - 8.5 Units ns ns ns ns ns ns PCLK cycles CLK cycles CLK cycles ns ns ns ns ns 6s tODS 6p tODP 7 8 9 10 11 12 13 tRWH tWK tDLY tCYCLE_PS Clock Cycle for PSOUTp, PSOUTn clock tPWH_PS tPWL_PS tOD_PS PSOUT Clock Pulse Width HIGH PSOUT Clock Pulse Width LOW Output Delay from PSOUT 1. Minimum Fs (sampling clock = 30 MHz). L64733/L64734 Tuner and Satellite Receiver Chipset 39 L64733/34 Chipset Ordering and Part Marking Information The L64733 and the L64734 are ordered as a set. Table 12 gives ordering information for the chipset. Table 12 L64733/34 Chipset Ordering Information Package Type 48-pin TQFP 100-pin PQFPt Operating Range Commercial Commercial Order Number L64733B L64734C-45 Table 13 gives part marking information for the two chips. Table 13 Part L64733 rev. B L64733 and L64734 Part Marking Information Production Chip Marking LSI 64733 MAX2104 YYWW+ESD MAXIM LSI L64734C-45 DBS Receiver FMA YYWW+ESD Assy Lot # 65060A1 OAS515U4FAA Country of Origin L64734 rev. C The tables and figures that follow provide pinouts and mechanical drawings for each package in the chipset. 40 L64733/L64734 Tuner and Satellite Receiver Chipset L64733 Pinout and Packaging Information Pinouts Figure 14 gives the pinout for the 48-pin TQFP L64733 package. Figure 14 L64733 48-Pin TQFP Pinout PLLINn PLLINp MODn MODp GND IOUTp IOUTn VCC QOUTp QOUTn FDOUB FLCLK PSOUTp PSOUTn VCC GND GND TANKn VRLO TANKp VCC GND FB CP L64733/L64734 Tuner and Satellite Receiver Chipset VCC CFLT XTLn XTLp GND VCC RFINn RFINp GND GNDSUB QDCn QDCp 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Top View INSEL AGC2 AGC1 CPG2 XTLOUT VCC CPG1 RFOUT GND GNDSUB IDCp IDCn 41 Mechanical Drawing Figure 15 is a mechanical drawing for the 48-pin TQFP L64733 package. Figure 15 L64733 48-Pin TQFP Mechanical Drawing TOP VIEW D D/2 D1 D1/2 E1/2 A e E E1 .15 MIN. BOTTOM VIEW .50 MAX. EXPOSED PAD CORNER TAB DETAIL EVEN LEAD SIDES E/2 SEE DETAIL "A" e/2 8 PLACES 11-13 A 0 MIN. M DATUM PLANE -H0.08 R. MIN. 0-7 0.20 MIN. 0.09/0.20 b 0.09/0.16 1.00 REF. DETAIL "B" L DETAIL "A" SEE DETAIL "B" A2 0.08/0.20 R. 0.25 GAUGE PLANE b WITH LEAD FINISH A1 1 BASE METAL Notes: 1. All dimensioning and tolerancing conform to Ansi Y14.5-1982. 2. Datum plane - H - is located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Dimensions D1 and E1 do not include mold protrusion. allowable mold protrusion is 0.254 mm on D1 and E1 dimensions. 4. The top of package is smaller than the bottom of package by 0.15 millimeters. 5. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the B dimension at maximum material condition. 6. Controlling dimension: millimeter. 7. Maximum allowable die thickness to be assembled in this package family is 0.30 millimeters. 8. This outline conforms to Jedec Publication 95 Registration MO-136, variations AC and AE. 9. Exposed die pad shall be coplanar with bottom of package within 2 mils (0.05 mm). 10. Metal area of exposed die pad shall be within 0.3 mm of the nominal die pad size. S Y M B O L JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS AE MIN. 0.05 0.95 NOM. 0.10 1.00 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.60 48 0.5 BSC. 0.22 0.20 MAX. 1.20 0.15 1.05 A A1 A2 D D1 E E1 L M N e b b1 0.45 0.14 0.17 0.17 0.75 0.27 0.23 42 L64733/L64734 Tuner and Satellite Receiver Chipset L64734 Pinout and Packaging Information Pinouts Figure 16 gives the pinout for the 100-pin PQFPt L64734 package. Figure 16 L64734 100-Pin PQFPt Pinout VSS VDD PLLVSS LP2 PLLAGND PLLVDD PCLK LCLK VSS VDD CO[0] CO[1] CO[2] CO[3] VSS VDD CO[4] CO[5] CO[6] CO[7] VSS VDD BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn VSS VDD COEn IDDTn 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VDD VSS ADCVDDI IVINp IVINn ADCVSSI VREFP VMID VREFN ADCVDDQ QVINp QVINn ADCVSSQ VDD VSS FDOUB FLCLK INSEL AGC2 AGC1 VDD VSS XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN VDD VSS IBYPASS[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SADR[1] SADR[0] VDD VSS SDATA SCLK INTn RESET VDD VSS PSOUTn PSOUTp VDD VSS PLLINn PLLINp RESO_LVDS VREF_LVDS MODn MODp Top View XOOUT XOIN VSS CLK VDD QBYPASS[0] QBYPASS[1] VSS VDD QBYPASS[2] QBYPASS[3] QBYPASS[4] QBYPASS[5] IBYPASS[0] VSS VDD IBYPASS[1] IBYPASS[2] IBYPASS[3] IBYPASS[4] L64733/L64734 Tuner and Satellite Receiver Chipset 43 Mechanical Drawings Figure 17 is a mechanical drawing for the 100-pin PQFPt L64734 package. Figure 17 100-Pin PQFPt (U4) Mechanical Drawing Important: This drawing might not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code U4. 44 L64733/L64734 Tuner and Satellite Receiver Chipset Figure 17 100-Pin PQFPt (U4) Mechanical Drawing (Cont.) Important: This drawing might not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code U4. L64733/L64734 Tuner and Satellite Receiver Chipset 45 Notes 46 L64733/L64734 Tuner and Satellite Receiver Chipset Notes L64733/L64734 Tuner and Satellite Receiver Chipset 47 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters Tel: 408.433.8000 Fax: 408.433.8989 NORTH AMERICA California Irvine Tel: 949.809.4600 Fax: 949.809.4444 Pleasanton Design Center Tel: 925.730.8800 Fax: 925.730.8700 San Diego Tel: 858.467.6981 Fax: 858.496.0548 Silicon Valley Tel: 408.433.8000 Fax: 408.954.3353 Wireless Design Center Tel: 858.350.5560 Fax: 858.350.0171 Colorado Boulder Tel: 303.447.3800 Fax: 303.541.0641 Colorado Springs Tel: 719.533.7000 Fax: 719.533.7020 Fort Collins Tel: 970.223.5100 Fax: 970.206.5549 Florida Boca Raton Tel: 561.989.3236 Fax: 561.989.3237 Georgia Alpharetta Tel: 770.753.6146 Fax: 770.753.6147 Illinois Oakbrook Terrace Tel: 630.954.2234 Fax: 630.954.2235 Kentucky Bowling Green Tel: 270.793.0010 Fax: 270.793.0040 Maryland Bethesda Tel: 301.897.5800 Fax: 301.897.8389 Massachusetts Waltham Tel: 781.890.0180 Fax: 781.890.6158 Burlington - Mint Technology Tel: 781.685.3800 Fax: 781.685.3801 Minnesota Minneapolis Tel: 612.921.8300 Fax: 612.921.8399 New Jersey Red Bank Tel: 732.933.2656 Fax: 732.933.2643 Cherry Hill - Mint Technology Tel: 856.489.5530 Fax: 856.489.5531 New York Fairport Tel: 716.218.0020 Fax: 716.218.9010 North Carolina Raleigh Tel: 919.785.4520 Fax: 919.783.8909 Oregon Beaverton Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin Tel: 512.388.7294 Fax: 512.388.4171 Korea Seoul LSI Logic Corporation of Korea Ltd Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd Tel: 31.40.265.3580 Fax: 31.40.296.2109 Singapore Singapore LSI Logic Pte Ltd Tel: 65.334.9061 Fax: 65.334.4749 Sweden Stockholm LSI Logic AB Tel: 46.8.444.15.00 Fax: 46.8.750.66.47 Taiwan Taipei LSI Logic Asia, Inc. Taiwan Branch Tel: 886.2.2718.7828 Fax: 886.2.2718.8869 United Kingdom Bracknell LSI Logic Europe Ltd Tel: 44.1344.426544 Fax: 44.1344.481039 Tel: 972.244.5000 Plano Fax: 972.244.5001 Houston Tel: 281.379.7800 Fax: 281.379.7818 Canada Ontario Ottawa Tel: 613.592.1263 Fax: 613.592.3253 INTERNATIONAL France Paris LSI Logic S.A. Immeuble Europa Tel: 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 Germany Munich LSI Logic GmbH Tel: 49.89.4.58.33.0 Fax: 49.89.4.58.33.108 Tel: 49.711.13.96.90 Stuttgart Fax: 49.711.86.61.428 Italy Milan LSI Logic S.P.A. Tel: 39.039.687371 Fax: 39.039.6057867 Japan Tokyo LSI Logic K.K. Tel: 81.3.5463.7821 Fax: 81.3.5463.7820 Sales Offices with Design Resource Centers Tel: 81.6.947.5281 Osaka Fax: 81.6.947.5287 To receive product literature, visit us at http://www.lsilogic.com ISO 9000 Certified Printed on Recycled Paper DR Printed in USA Order No. I15041 Doc. No. DB08-000102-01 The LSI Logic logo design is a registered trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or of third parties. |
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